1. Field of the Invention
This invention is related to the field of scan functionality in integrated circuits, and specifically to inserting scan functionality during the design of an integrated circuit.
2. Description of the Related Art
As integrated circuit fabrication process technology has continued to shrink the size of transistors and other circuitry on an integrated circuit, the number of transistors and other circuitry has continued to increase. Additionally, the potential for manufacturing defects to occur that cause incorrect operation continues to increase. The importance of testability in the integrated circuit has therefore continued to increase.
An important part of design for test (DFT) methodologies is scan functionality. Generally, all of the clocked storage devices in the integrated circuits (e.g. flops, registers, latches, etc.) are designed with scan functionality so that the devices can be connected together in scan chains. During scan operation, known test data can be scanned into the devices. Once the test data is scanned in, at least one functional clock cycle can be performed. The circuitry that is connected to the devices evaluates in response to the test data, and the result is captured in the functional clock cycle(s). The result can then be scanned out and compared to expected data that should be generated if there are no manufacturing defects. With enough test data, most if not all of the integrated circuit can be tested to ensure high quality integrated circuits are delivered to customers.
The scan chains are created and connected to integrated circuit inputs and outputs via scan circuitry. In many cases, the scan logic and the connection of scan chains can be large, and impacts the ability to complete the integrated circuit design in a desired semiconductor substrate area. Additionally, at least some of the scan logic and connectivity is typically inserted late in the design process. Increasing the area between blocks of circuitry in the integrated circuit late in the process can create functional timing issues and other problems that slow design closure and completion. Typical scan insertion tools receive a list of scan chain inputs and outputs and generate register-transfer level (RTL) descriptions of the scan logic and interconnect based on the list.